Presently, SARM power consumption is mainly reduced by introducing replica bit-line control circuit 100 to SRAM to produce sensitivity amplifier enabling signals SAE and wordline control signals WL. The schematic block diagram is as shown in FIG. 1. A replica bit-line control circuit is proposed by Amrutur B S, Horowitz M. in A replica technique for wordline and sense control in low-power SRAM's [J]. IEEE Journal of Solid-State Circuits, 1998, 33(8): 1208, which is as shown in FIG. 2. When sense amplifier enabling signals are valid, wordline control signal WL of the replica bit-line control circuit is to be cut off through time delay by the inverter S9 and NOR gate D1, which may further result in unnecessary voltage loss; furthermore, a feedback oscillation is to be produced when chip selection signal BS is set at high electrical level for a prolonged time, which may continuously charge and discharge the capacitor of replica wordline signal RWL and replica bit-line RBL to the extent of incurring unnecessary power consumption; the feedback oscillation waveform is as shown in FIG. 3.